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AD9695BCPZ-1300上海通信IC 鸿科伟业现货

AD9695BCPZ-1300上海通信IC 鸿科伟业现货

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AD9695BCPZ-1300和AD9162BBCZ的对比

The AD9695 is a dual, 14-bit, 1300 MSPS/625 MSPS analog-todigital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 2 GHz. The ?3 dB bandwidth of the ADC input is 2 GHz. The AD9695 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.


The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of multiple signal processing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and decimation filters. The NCO has the option to select up to 16 preset bands over the general-purpose input/output (GPIO) pins, or use a coherent fast frequency hopping mechanism for band selection. Operation of the AD9695 between the DDC modes is selectable via SPI-programmable profiles.


In addition to the DDC blocks, the AD9695 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9695 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.


The user can configure the Subclasss 1 JESD204B-based high speed serialized output using either one lane, two lanes, or four lanes, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF± and SYNCINB± input pins. The AD9695 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 3-wire serial port interface (SPI) and or PDWN/STBY pin.


The AD9695 is available in a Pb-free, 64-lead LFCSP and is specified over the ?40°C to +105°C junction temperature range. This product may be protected by one or more U.S. or international patents.


Note that, throughout this data sheet, multifunction pins, such as FD_A/GPIO_A0, are referred to either by the entire pin name or by a single function of the pin, for example, FD_A, when only that function is relevant.


Product Highlights


Low power consumption per channel.

JESD204B lane rate support up to 16 Gbps.

Wide, full power bandwidth supports intermediate

frequency (IF) sampling of signals up to 2 GHz.

Buffered inputs ease filter design and implementation.

Four integrated wideband decimation filters and NCO

blocks supporting multiband receivers.

Programmable fast overrange detection.

On-chip temperature diode for system thermal management.

Applications


Communications

Diversity multiband, multimode digital receivers

3G/4G, TD-SCDMA, WCDMA, GSM, LTE

General-purpose software radios

Ultrawideband satellite receiver

Instrumentation

Oscilloscopes

Spectrum analyzers

Network analyzers

Integrated RF test solutions

Radar

Electronic support measures, electronic counter measures, and electronic counter-counter measures

High speed data acquisition systems

DOCSIS 3.0 CMTS upstream receive paths

Hybrid fiber coaxial digital reverse path receivers

Wideband digital predistortion

AD9695是一种双、14位、1300 MSPS/625 MSPS模数转换器(ADC)。该器件具有片上缓冲器和为低功耗、小尺寸和易用性而设计的采样保持电路。该产品被设计为支持能够直接采样高达2 GHz的宽带模拟信号的通信应用。ADC输入的3分贝带宽为2 GHz。AD9695在宽的输入带宽、高的采样率、良好的线性度以及小封装的低功耗下得到了优化。

双ADC核具有多级、差分流水线结构,具有集成的输出纠错逻辑。每个ADC具有支持多种用户可选择输入范围的宽带输入。集成的电压基准简化了设计考虑。模拟输入和时钟信号是差分输入。ADC数据输出通过纵横复用器内部连接到四个数字下变频器(DDCS)。每个DDC由多个信号处理阶段组成:48位频率转换器(数控振荡器(NCO))和抽取滤波器。NCO可选择在通用输入/输出(GPIO)引脚上选择多达16个预置频带,或使用相干快速跳频机制进行频带选择。AD9695在DDC模式之间的操作可通过SPI可编程配置文件来选择。

除了DDC块之外,AD9695还具有简化通信接收机中的自动增益控制(AGC)功能的若干功能。可编程门限检测器允许使用ADC寄存器0x0245中的快速检测控制位来监视输入信号功率。如果输入信号电平超过可编程阈值,则快速检测指示器变高。由于该阈值指示器具有低延迟,用户可以快速地关闭系统增益以避免ADC输入处的超范围条件。除了快速检测输出外,AD9695还提供信号监测能力。信号监视块提供关于由ADC数字化的信号的附加信息。

用户可以根据接收逻辑设备的DDC配置和可接受的车道率,使用基于一条车道、两条车道或四条车道的高速串行化输出来配置子类1 JESD204B。多设备同步通过SysReF±和ScCYNB±输入引脚来支持。AD9695具有灵活的掉电选项,在需要时允许显著的功率节省。所有这些功能可以使用3线串行端口接口(SPI)和PDWN/STBY引脚编程。

AD9695可在无铅、64引脚LFCSP中使用,并在40°C至+105°C交界温度范围内指定。该产品可由一个或多个美国或国际专利保护。

请注意,在整个数据表中,多功能引脚,例如FDYA/GPIOYA0,是指由整个PIN名称或由PIN的单一功能,例如FDFA,当只有该函数是相关的。

产品亮点

低功耗每通道。

JESD204B车道率支持高达16 Gbps。

宽,全功率带宽支持中间

频率(IF)采样高达2 GHz的信号。

缓冲输入简化滤波器的设计和实现。

四集成宽带抽取滤波器和NCO

支持多频带接收机的块。

可编程快速超范围检测。

用于系统热管理的片上温度二极管。

应用

通信

分集多频带多模数字接收机

3G/4G、TD-SCDMA、WCDMA、GSM、LTE

通用软件无线电

超宽带卫星接收机

仪器仪表

示波器

频谱分析仪

网络分析

集成射频测试解决方案

雷达

电子支援措施、电子对抗措施及电子对抗措施

高速数据采集系统

DOCSIS 3 CMTS上行接收路径

混合光纤同轴数字反向通路接收机

宽带数字预失真


AD9695BCPZ-1300的特征


JESD204B(子类1)编码串行数字输出

车道率高达16 Gbps

1.6瓦总功率在1300 MSPS

每ADC通道800兆瓦

SNR=65.6 dBFs,在172 MHz(1.59 V P P输入范围)

SFDR=78兆赫(172.3兆赫)(1.59 V P P输入范围)

噪声密度

- 153.9 dBFS/Hz(1.59 V P P输入范围)

- 155.6 dBFS/Hz(2.04 V P P输入范围)

0.95伏,1.8伏,2.5伏供电操作

无遗失码

内部模数转换器基准电压

柔性输入范围

1.36 V p p到2.04 V p p(1.59 V p p典型)

2 GHz可用模拟输入全功率带宽

>95分贝通道隔离/串扰

用于有效AGC实现的幅度检测位

2个ADC通道的集成数字下变频器

48位NCO

可编程抽取率

差分时钟输入

SPI控制

整数时钟除以2除以4

灵活的JESD204B车道配置

片上抖动改善小信号线性度

AD9162BBCZ 

16-Bit, 12 GSPS, RF Digital-to-Analog Converters 

产品详情

AD9162是一款高性能16位数模转换器(DAC),支持达6 GSPS的数据速率。DAC内核基于一个四通道开关结构配合2倍插值滤波器,使DAC的有效更新速率在某些模式下高达12 GSPS。高动态范围和带宽使这些DAC非常适合***苛刻的高速射频(RF)DAC应用。

在基带模式下,元件的宽带宽能力和高动态范围相结合,在***小两个载波至1.794 GHz的满量程频谱范围内可支持DOCSIS 3.1电缆基础设施兼容性。2倍插值滤波器(FIR85)使AD9161/AD9162针对较低数据速率和转换器时钟进行配置,可降低系统总体功耗和滤波要求。在Mix-Mode 操作模式中,AD9161/ AD9162可在高达7.5 GHz的二阶和三阶奈奎斯特区内重构RF载波,同时仍保持出色的动态范围。输出电流可以在8 mA至38.76 mA范围内进行编程。AD9161/AD9162数据接口由***多八个JESD204B串行器/解串器(SERDES)通道组成,可对其通道速度和通道数进行编程,从而实现应用灵活性。

串行外设接口(SPI)可配置AD9162并监控所有寄存器的状态。AD9162提供165引脚、8.0 mm × 8.0 mm、0.5 mm间距、CSP_BGA和169引脚、11 mm × 11 mm、0.8 mm间距、CSP_BGA两种封装,包括引脚选项。

产品特色

  1. 高动态范围和信号重建带宽支持高达7.5 GHz的RF信号频率合成。

  2. 高达八个通道JESD204B SERDES接口,支持灵活的通道数和通道速度。

  3. 带宽和动态范围可满足DOCSIS 3.1余量兼容性要求。



SMJ320C25FDM

This data sheet provides design documentation for the SMJ320C25 and the SMJ320C25-50 digital signal processor (DSP) devices in the SMJ320 family of VLSI digital signal processors and peripherals. The SMJ320 family supports a wide range of digital signal processing applications such as tactical communications, guidance, military modems, speech processing, spectrum analysis, audio processing, digital filtering, high-speed control, graphics, and other computation-intensive applications.

Differences between the SMJ320C25 and the SMJ320C25-50 are specifically identified, as in the following paragraph and in the parameter tables on pages 18 through 24 of this data sheet. When not specifically differentiated, the term SMJ320C25 is used to describe both devices.

The SMJ320C25 has a 100-ns instruction cycle time. The SMJ320C25-50 has an 80-ns instruction cycle time. With these fast instruction cycle times and their innovative memory configurations, these devices perform operations necessary for many real-time digital signal processing algorithms. Since most instructions require only one cycle, the SMJ320C25 is capable of executing 12.5 million instructions per second. On-chip data RAM of 544 16-bit words, on-chip program ROM of 4K words, direct addressing of up to 64K words of external data memory space and 64K words of external program memory space, and multiprocessor interface features for sharing global memory minimize unnecessary data transfers to take full advantage of the capabilities of the instruction set.


Key Features

  • Military Temperature Range

    • -55°C to 125°C

  • 100-ns or 80-ns Instruction Cycle Times

  • 544 Words of Programmable On-Chip Data RAM

  • 4K Words of On-Chip Program ROM

  • 128K Words of Data/Program Space

  • 16 Input and 16 Output Channels

  • 16-Bit Parallel Interface

  • Directly Accessible External Data Memory Space

    • Global Data Memory Interface

  • 16-Bit Instruction and Data Words

  • 16 × 16-Bit Multiplier With a 32-Bit Product

  • 32-Bit ALU and Accumulator

  • Single-Cycle Multiply/Accumulate Instructions

  • 0 to 16-Bit Scaling Shifter

  • Bit Manipulation and Logical Instructions

  • Instruction Set Support for Floating-Point Operations, Adaptive Filtering, and Extended-Precision Arithmetic

  • Block Moves for Data/Program Management

  • Repeat Instructions for Efficient Use of Program Space

  • Eight Auxiliary Registers and Dedicated Arithmetic Unit for Indirect Addressing

  • Serial Port for Direct Code Interface

  • Synchronization Input for Synchronous Multiprocessor Configurations

  • Wait States for Communication to Slow-Off-Chip Memories/Peripherals

  • On-Chip Timer for Control Operations

  • Three External Maskable User Interrupts

  • Input Pin Polled by Software Branch Instruction

  • 1.6-um CMOS Technology

  • Programmable Output Pin for Signaling External Devices

  • Single 5-V Supply

  • On-Chip Clock Generator

  • Packaging:

    • 68-Pin Leaded Ceramic Chip Carrier (FJ Suffix)

    • 68-Pin Ceramic Grid Array (GB Suffix)

    • 68-Pin Leadless Ceramic Chip Carrier (FD Suffix)



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